Switching capacitive DC-DC voltage converters typically use “flying capacitors”. These capacitors are charged from the input voltage and then discharged to the load thus providing charge transfer and a constant output voltage.
FIG. 1 shows a basic known DC-DC converter circuit.
The circuit comprises a switching capacitor Csw. One terminal SAP is connected to the input through a first switch S1 and to the output through a third switch S3. The other terminal SAM is connected to the input through a fourth switch S4 and to ground through a second switch S2.
Basic DC-DC converters of this type integrate switches S1 to S4 and an oscillator so that the switches work alternately in pairs S1,S2 and S3,S4.
The oscillator output is shown as a clock signal Clk, and it is passed to the switches in dependence on whether the output voltage VOUT has reached a target voltage Vref. An AND gate 10 controls the passing of the clock signal, and a comparator compares the output voltage (or a voltage derived from the output voltage) with the reference level Vref. The comparator output is used to control whether the AND gate passes the clock signal. The comparator output is thus a control signal PUMP which controls the converter pumping. When it is high, the cyclic charge pumping is enabled, and when it is low, the cycles are halted,
The configuration shown doubles the input voltage.
The DC-DC converter operates in two phases, sequenced by the clock. Closing switches S1 and S2 charges the flying capacitor Csw to the input voltage Vin in a first half cycle (storing phase). In the second half cycle, switches S3 and S4 close and switches S1 and S2 open (loading phase). This action connects the negative terminal SAM of Csw to Vin and connects the positive terminal SAP to VOUT. If the voltage across the output load Cload is smaller than that across Csw, charge flows from Csw to Cload.
The storing phase and loading phase occur alternately, boosting the DC-DC converter output voltage until its target value Vref is reached. When VOUT reaches Vref, the switching clock is stopped, and then the DC-DC converter stays in the storing phase.
As soon VOUT goes below Vref, the DC-DC converter restarts pumping, alternating the storing and loading phases until VOUT again rises above Vref.
The DC-DC converter output voltage should be regulated within a voltage window by using a voltage hysteresis of the comparator 12. In this way, VOUT is regulated between Vref and Vref+Hyst. The threshold voltage for the VOUT rising edge is Vref+Hyst, and the threshold voltage for the falling edge is Vref.
FIG. 2 shows this operation, and shows the voltage waveform of the output voltage VOUT, which fluctuates between Vref and Vref+Hyst.
During a start-up time, the DC-DC converter pumps energy from Vin to VOUT, and VOUT rises to Vref+Hyst. The DC-DC converter then stops by staying in a storing state. This is shown as phase P1, and it corresponds the signal PUMP being low, waiting for the output voltage to drop back to Vref.
During phase P1, VOUT falls linearly due to the output load current until Vref, and then the DC-DC converter restarts to boost VOUT until Vref+Hyst. This boosting involves alternate loading phases P2 and storing phase P3.
This application relates in particular to the transient behaviour of the circuit. FIG. 3 shows the storing P3 and loading P2 phases of the circuit including the on-resistances of the switches.
The transient behaviour of the output VOUT and the capacitor terminals SAP and SAM over three phases (store P3, then load P2, then store P3) is shown in FIG. 4, taking account of the resistive elements.
FIG. 4 is a zoom in to the output voltage VOUT when the DC-DC converter is in steady state. Thus, the time t=0 is simply used to provide a reference point at which voltages VOUT0 and SAM0 are defined.
The maximum voltage SAPmax on on the node SAP is shortly after the beginning of phase P2 (i.e. a short time ε after the reference time t=0). At the beginning of each phase, the flying capacitor can be considered as a short circuit.
Thus, the circuit configuration when switching from phase P3 to P2 is as shown in FIG. 5.
At t=0, the voltage on terminal SAM is equal to VOUT divided by two. The maximum voltage SAPmax is given by SAM0 plus VIN. So the maximum voltage is equal to:SAPmax=VOUT0/2+VIN
The model used to create the timing diagrams of FIG. 4 is based on the simulation of an ideal DC-DC converter. However, in reality during the switching transition phase a higher voltage is seen on the SAP pin. This difference between a real silicon device and the model can be explained by introducing parasitic variables.
By introducing parasitic variables derived from the DC-DC converter power switches and from the output electrical line, the initial condition on SAM before phase P2 is modified.
FIG. 6 shows the circuit with parasitic capacitances and inductances added.
The added parasitics are defined as followed:
(i) The serial inductance between the DC-DC converter integrated circuit output and the external output capacitor is modeled as an inductance, Lout. Its charge induces an overshoot on SAP. Its time constant is defined as:
      τ    L    =            L      out              R      on      
(ii) The gate of the DC-DC power switches are modeled as a capacitance. Their sum seen on SAM pin is named Cgate. It limits the overshoot on SAP. Its time constant is defined as:τgate=Ron×Cgate 
In this condition, the maximum voltage on DC-DC converter SAP pin can be shown to be:
      SAP    0    =                              VUP          0                2            ×              (                  1          -                                    τ              gate                                                      τ                L                            +                              τ                gate                                                    )            ×              (                  1          +                                    (                                                τ                  gate                                                                      τ                    L                                    +                                      τ                    gate                                                              )                                                      τ                gate                                            τ                L                                                    )              +    VIN  
This formula derives from a circuit analysis of FIG. 6.
FIG. 7 shows the maximum voltage on the DC-DC converter SAP pin (value SAPmax at time t=ε) versus the parasitic serial inductance. This example is given for 4.5V input voltage, 5.5V output and a 1 nF gate parasitic gate capacitance. The switching capacitor Csw in this example is 330 nF and the load capacitor is 250 nF. The on resistance RON is modeled as 0.5 Ω.
This example shows two main issues:
(i) A large range of DC-DC maximum voltage from 7.25V to 9.5V is obtained as a function of the parasitic inductance.
(ii) There is no possibility for the customer to reduce the DC-DC maximum voltage by playing with COUT or CSW.
In fact, this maximum appears as an overshoot just at the beginning of the store (i.e. discharging) phase P3.
FIG. 8 shows the transient behaviour of the capacitor terminal pins with and without parasitics. The solid SAP and SAM lines are with parasitics and the dashed lines are without.
This overshoot is critical to the DC-DC converter operation as it generates noise (EMC and switching noise). Therefore it adds design constraints on the DC-DC converter implementation as the DC-DC internal components should handle the electrical overstress. The DC-DC converter electrical performance is more dependent on the customer application than the silicon.